This application claims the priority benefit of Taiwan application serial no. 91134042, filed Nov. 22, 2002.
1. Field of Invention
The present invention relates to a thin film transistor array and driving circuit structure. More particularly, the present invention relates to a thin film transistor array and driving circuit structure that can be fabricated in six masking steps.
2. Description of Related Art
In recent years, the rapid advance in the fabrication of semiconductor devices and display devices has lead to the popularization of multimedia systems. Due to the production of high-quality and low-cost displays such as cathode ray tubes, these displays now represent a large chunk in the display market. However, from the standpoint of a desktop display user or an environmentalist, a cathode ray tube is bulky, consumes a lot of energy and is also a source of radiation. Since a lot of material is required to fabricate each cathode ray tube and a lot of energy is wasted in its operation, other types of displays including thin film transistor liquid crystal display (TFT-LCD) have been developed as a substitute. A conventional TFT-LCD is a slim and compact display capable of producing high-quality images. Each TFT-LCD uses very little energy and is virtually radiation-free. All these advantages have championed the TFT-LCD in the mainstream display market.
In general, a thin film transistor may be classified as an amorphous thin film transistor or a polysilicon thin film transistor. A polysilicon thin film transistor fabricated using a low-temperature polysilicon (LTPS) technique is different from an amorphous thin film transistor using an amorphous silicon (a-Si) technique. The LTPS transistor has an electron mobility greater than 200 cm2/V-sec and hence the thin film transistor can have a smaller dimension, a larger aperture ratio and a lower power rating. In addition, the LTPS process also permits the concurrent fabrication of a portion of the driving circuit and the thin film transistor in the same substrate so that the subsequently formed liquid crystal display panel has a greater reliability and a lower average production cost.
FIGS. 1A to 1H are schematic cross-sectional views showing the progression of steps for fabricating a conventional thin film transistor array and driving circuit. As shown in FIG. 1A, a substrate 100 is provided. A polysilicon layer is formed over the substrate 100. Thereafter, the polysilicon layer is patterned using a first masking process (Mask 1) so that a plurality of poly-islands 102a, 102b and 102c are formed over the substrate 100. The poly-island 102a is a location for forming a thin film transistor while the poly-islands 102b and 102c are locations for forming a driving circuit such as a complementary metal-oxide-semiconductor (CMOS) circuit. Since the poly-island 102a is eventually transformed into a thin film transistor, poly-islands 102a are normally positioned on top of the substrate 100 as an array. Similarly, since the poly-islands 102b and 102c are eventually transformed into driving circuits, the poly-islands 102b and 102c are normally positioned close to the peripheral region of the substrate 100.
As shown in FIG. 1B, a first dielectric layer 104 and a conductive layer (not shown) are sequentially formed over the substrate 100 with the poly-islands 102a, 102b and 102c thereon. The conductive layer is patterned using a second masking process (Mask 2) to form gates 106a, 106b and 106c over the poly-islands 102a, 102b and 102c respectively and the lower electrode 108 of a storage capacity on a suitable location on the substrate 100.
As shown in FIG. 1C, N+ doped regions 110 and N+ doped regions 112 are patterned out inside the island 102a and the island 102c using a third masking process (Mask 3). The N+ doped regions 110 inside the island 102a is located on each side of the gate 106a and the N+ doped regions 112 inside the island 102c are located on each side of the gate 106c. 
As shown in FIG. 1D, Nxe2x88x92 doped regions 114 are patterned inside the island 102a and Nxe2x88x92 doped regions 116 are patterned inside the island 102c using a fourth masking process (Mask 4). Each Nxe2x88x92 doped region 114 inside the island 102a is located between the gate 106a and one N+ doped region 110. Similarly, each Nxe2x88x92 doped region 116 inside the island 102c is located between the gate 106c and one N+ doped region 112.
As shown in FIG. 1E, P+ doped regions 118 are patterned inside the island 102b using a fifth masking process (Mask 5). The P+ doped regions 118 inside the island 102b are located on each side of the gate 106b. 
As shown in FIG. 1F, a second dielectric layer 120 is formed over the substrate 100. Thereafter, the first dielectric layer 104 and the second dielectric layer 120 are patterned using a sixth masking process (Mask 6) to form openings 122a, 122b and 122c. The opening 122a exposes the N+ doped region 110, the opening 122b exposes the P+ doped region 118 and the opening 122c exposes the N+ doped region 112.
As shown in FIG. 1G, a conductive layer (not shown) is formed over the second dielectric layer 120. Thereafter, the conductive layer is patterned using a seventh masking process (Mask 7) to form source/drain terminals 124 (comprising 124a, 124b and 124c respectively). The source/drain terminals 124 are electrically connected to the N+ doped region 110, the P+ doped region 118 and the N+ doped region 112 through the opening 122a, the opening 122b and the opening 122c respectively.
As shown in FIG. 1H, a planarization layer 126 is formed over the substrate 100 with the source/drain terminals 124 thereon. Thereafter, the planarization layer 126 is patterned using an eighth masking process (Mask 8) to form an opening 128 for exposing the source/drain terminal 124a. After patterning the planarization layer 126, a conductive layer (not shown) is formed over the substrate 100. The conductive layer is a transparent layer typically made from indium-tin-oxide material. The conductive layer is patterned using a ninth masking process (Mask 9) to form a pixel electrode 130.
As shown on the left side of FIG. 1H, the Nxe2x88x92 doped region 116 and the N+ doped region 112 inside the island 102c, the gate 106c and the source/drain terminal 124c together constitute an N-type metal-oxide-semiconductor (NMOS) transistor. The P+ doped region 18 inside the island 102b, the gate 106b and the source/drain terminal 124b together constitute a P-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor and the PMOS transistor together constitute a complementary metal-oxide-semiconductor (CMOS) transistor. The CMOS transistor on the substrate 100 is a driving circuit for driving the thin film transistor on the right side of FIG. 1H and hence controlling the pixel display.
As shown on the right side of FIG. 1H, the Nxe2x88x92 doped region 110 and the N+ doped region 114 inside the island 102a, the gate 106a and the source/drain terminal 124a together constitute a polysilicon thin film transistor (poly-TFT). The writing of data into the pixel electrode 120 of the thin film transistor is driven and controlled by the CMOS.
FIG. 2 is a flow chart showing the steps for fabricating a conventional thin film transistor array and driving circuit. As shown in FIG. 2, the process of fabricating the thin film transistor array and the driving circuit includes: patterning a polysilicon layer (S200); patterning out a gate and the lower electrode of a storage capacitor (S202); patterning out a N+ doped region (S204), patterning out an Nxe2x88x92 doped region (S206); patterning out a P+ doped region (S208), patterning out a first dielectric layer (S210); patterning out source/drain terminals and the upper electrode of the storage capacitor (S212); patterning a second dielectric layer (S214) and patterning out a pixel electrode (S216).
To fabricate the structure of a conventional thin film transistor array and driving circuits, as much as eight masking steps (not including the fabrication of the Nxe2x88x92 doped regions 114 and 116) or nine masking steps are required. This leads to a relatively high production cost. In addition, the greater number of masking steps also leads to a longer production time and a lower production yield.
Accordingly, one object of the present invention is to provide a thin film transistor array and driving circuit structure that can be fabricated in only six masking steps.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a thin film transistor array and driving circuit structure fabricated on a substrate. The structure mainly comprises a plurality of scanning lines, a plurality of signal lines, a plurality of thin film transistors, a plurality of pixel electrodes, a plurality of storage capacitors and a plurality of complementary metal-oxide-semiconductor (CMOS) transistors.
In this invention, the thin film transistor comprises a polysilicon layer, a source/drain terminal, an N+ doped thin film, a gate and a gate insulation layer. The polysilicon layer is formed over the substrate and the source/drain terminal is formed over the polysilicon layer. The N+ doped thin film is positioned between the polysilicon layer and the source/drain terminal. The gate is formed over the polysilicon layer and the gate insulation layer is positioned between polysilicon layer and the gate.
In this invention, the pixel electrode and the storage capacitor are formed on the substrate to correspond with the thin film transistor.
In this invention, the CMOS transistor includes an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor. The NMOS transistor comprises a polysilicon layer, a source/drain terminal, a N+ doped thin film, a gate and a gate insulation layer. The polysilicon layer is formed over the substrate and the source/drain terminal is formed over the polysilicon layer. The N+ doped thin film is positioned between the polysilicon layer and the source/drain terminal. The gate is formed over the polysilicon layer and the gate insulation layer is positioned between the polysilicon layer and the gate. In addition, the polysilicon layer between the gate and the source/drain terminal may further include an Nxe2x88x92 doped region.
The PMOS transistor comprises a polysilicon layer, a source/drain terminal, a P+ doped thin film, a gate and a gate insulation layer. The polysilicon layer is formed over the substrate and the source/drain terminal is formed over the polysilicon layer. The P+ doped thin film is positioned between the polysilicon layer and the source/drain terminal. The gate is formed over the polysilicon layer and the gate insulation layer is positioned between the polysilicon layer and the gate.
The aforementioned gate insulation layer includes at least one first dielectric layer. The first dielectric layer is made from a material such as silicon oxide, silicon nitride or hydrogen-containing dielectric material. In addition, the gate insulation layer may include at least one first dielectric layer and one second dielectric layer. The first dielectric layer is made from a material such as silicon oxide, silicon nitride or hydrogen-containing dielectric material. The second dielectric layer is made from a material such as a photosensitive resin.
In this invention, the gate is made from a material such as an aluminum/molybdenum alloy or an aluminum/titanium alloy. The source/drain terminal is made from a material such as an aluminum/molybdenum alloy or pure molybdenum.
For a transparent type of panel, the conductive layer can be made from a transparent conductive material such as indium-tin oxide. For a reflective type of panel, the conductive layer can be made from a metallic material with good reflective properties. In addition, the surface of a passivation layer underneath the conductive layer may be roughened to boost reflectivity of light from the conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.